In electronic systems with large switching or transient voltage spikes, linear voltage regulators are commonly employed to reject the spikes. However, when the spikes are large enough, voltage regulators can fail to reject those spikes. When large spikes occur, the conventional regulator output shows similar spikes, as shown in FIGS. 1-4. Spikes in the regulated voltage cause circuit malfunctions in the load circuits fed by the regulated voltage. For example, such spikes can cause the load circuits to reset and the like.
FIG. 1 shows a circuit that includes a conventional linear voltage regulator with a p-channel metal-oxide-semiconductor field-effect (PMOS) pass transistor M1. A current source I and resistor R0 provide an input reference voltage Vref to the positive input of an operational amplifier A. An n-channel MOS (NMOS) transistor M2 is configured as a diode to provide a bleeder current. In other embodiments, the bleeder current can be provided in other ways.
The source of transistor M1 receives supply voltage VDD. The gate of transistor M1 is connected to the output of operational amplifier A. The negative input of operational amplifier A is connected to the drain of transistor M1, and to the gate and drain of transistor M2. The drain of transistor M1 provides a regulated voltage Vreg to a load circuit 102.
The circuit of FIG. 1 includes a switching circuit 104 that causes large positive and negative voltage spikes in supply voltage VDD. FIG. 2 shows a plot of supply voltage VDD and regulated voltage Vreg over time t for the voltage regulator of FIG. 1. As can be seen in FIG. 2, the voltage regulator of FIG. 1 is unable to reject the spikes in supply voltage VDD, and so passes these spikes in regulated voltage Vreg.
In order to reject such voltage spikes, some conventional implementations include an RC filter. FIG. 3 shows a circuit that includes a conventional linear voltage regulator with an NMOS pass transistor M5 and a ground-referenced RC filter that includes a resistor R1 and a capacitor C. A current source I and resistor R0 provide an input reference voltage Vref to the positive input of operational amplifier A. Two NMOS transistors M4 and M6 are configured as respective diodes to provide bleeder currents. In other embodiments, the bleeder currents can be provided in other ways.
The drain of transistors M3 and M5 receive supply voltage VDD. The gate of transistor M3 is connected to the output of operational amplifier A. The negative input of operational amplifier A is connected to the source of transistor M3, and to the gate and drain of transistor M4. The gate of transistor M3 provides a bias voltage Vg. Resistor R1 and capacitor C filter bias voltage Vg, and thereby provide a filtered bias voltage Vgf.
The gate of pass transistor M5 receives filtered bias voltage Vgf. The source of transistor M5 is connected to the gate and drain of transistor M6. The source of transistor M5 provides a regulated voltage Vreg to load circuit 102.
FIG. 4 shows a plot of supply voltage VDD and regulated voltage Vreg over time t for the voltage regulator of FIG. 3. As can be seen in FIG. 4, the RC filter rejects positive voltage spikes in supply voltage VDD. However, the voltage regulator of FIG. 3 is unable to reject negative spikes in supply voltage VDD, and so passes these spikes in regulated voltage Vreg.